SRAM P-Mod for Digilent Basys 2 FPGA Board: Part 1


In this series, I’ll be covering the design and building of an SPI SRAM PMOD for the Digilent Basys2 FPGA Board.

This project came about more out of necessity than anything else. I want to design an 8-bit CPU on my FPGA board, but it has no RAM (other than the block ram in the FPGA, but it is very limited). Having searched and searched, I was unable to find a premade PMOD (the name that Digilent gives to expansion boards) that contained RAM, so I thought, “Hey! Why not make my own?”.

Choosing Parts

The first job was to source cheap, high-quality parts before I even attempted to design a PCB. I was lucky to find everything that I needed at Farnell. Lets have a look at our bill of materials:

As you can see, this isn’t exactly a very big project, which is good, because it accomplishes the task at hand without costing a fortune. The bill of materials cost is extremely low, working out at roughly ¬£12.26, which already includes the cost of the PCB. I’ve found an excellent PCB fabricator at OSH Park. They do large runs with multiple boards in order to keep costs down and end up costing far less than most other fabricators.

The Design

The design itself was not complicated. It was more a matter of joining the right leads on the IC up to the right pins on the PMOD header. No huge amounts of electronic engineering involved. About the only thing that required a little thought was the choice of filter capacitor. Here’s the finished design:

Eagle PCB design for SRAM PMOD
My SRAM PMOD design in eagle.
My SRAM PMOD design rendered by OSH Park.
My SRAM PMOD design rendered by OSH Park.

You might notice in my designe that the “Chip Select” pin (pin 1) is tied low at all times. This is because I don’t plan on disabling the chip at any time, and also because my Basys2 PMOD header doesn’t have enough I/O space to connect it anywhere else.

What Next?

This is as far as I am currently. After I receive my boards and components I’ll write another article showing it being assembled and tested. I’ll also include the eagle schematic and board files for download so you can build one yourself!

Until next time.


COEGen v0.01 – Generate .coe files from binary files for Xilinx FPGA block RAM.

What it Does

This is just a simple utility for creating .coe files to initialise Xilinx FPGA block ram. It takes an input file, typically binary data of some sort, and out puts ‘inputfilename’.coe.

You can even set the width of each memory block and the length of the memory.

How to Use

Using the program is pretty simple. Here’s an example:

 $ COEGen --file binary.bin --width 8 --depth 256 

This will output ‘binary.bin.coe’. This will initialise 256 bytes of 8-bit memory from the file binary.bin.

Note that if the specified memory size is larger than the input file, the rest of the block RAM will be filled with zeros.


The easiest way to get COEGen is to install a binary package. Here’s the link:



I’ve uploaded a build of COEGen for Windows.

You’ll need to use Code::Blocks to build it. The only dependencies are the boost libraries. How to get the source:

 $ git clone 

If you have any issues, feel free to contact me by commenting below. Enjoy!